One aspect of the invention relates to an integrated semiconductor chip having, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions.
Such integrated semiconductor chips which are constructed e.g., using high-voltage CMOS or BCD technology contain e.g., a plurality of power output stages together with a logic circuit region and/or an analog circuit region and/or, if appropriate, a flash memory. The power output stages are generally positioned at the chip edge in order to keep the resistances of the bonding connections as small as possible. The flash memory, which is generally the most sensitive to temperature, must for the most part lie in direct proximity to the output stages. Owing to the high electrical powers switched in the output stages, a very large amount of heat is developed here and thermally loads adjacent components, that is to say components of the temperature-sensitive semiconductor circuits. These thermal loadings essentially arise during switching operations and are therefore temporally limited. In the case of repetitive clamping, the switching operations last for 50 to 500 μs. If these operations last longer, the thermal switching losses generated are not as high. Generally, the temperature-sensitive components lying e.g., in the flash memory alongside the power output stages must not be exposed to temperatures higher than 150° C. By virtue of the advancing miniaturization of the CMOS transistors, in particular the PMOS transistors therein become more sensitive to temperature. Their voltage-temperature characteristic (VT) starts to shift.
In previously developed, commercially available integrated semiconductor chips, primarily to heat dissipations heat sinks are a tried and tested means for enabling the temperature of the entire semiconductor chip not to rise excessively. This was possible since the high-voltage processes had not yet been miniaturized to an extent such that temperature problems arose. High-voltage CMOS or BCD processes in the range of less than 250 nm will be developed in the future, however. For this reason, lateral thermal insulation measures on the integrated semiconductor chip at least between in each case the temperature-sensitive semiconductor circuit regions and the power semiconductor circuit region(s) are desirable or necessary.